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Design the FSMD (Finite State Machine with Datapath) that implements the following simple algorithm expressed in Python. The inputs a,b,c,d the variables $x$ are signed integers. You are free to design a Moore or a Mealy type FSMD. Specify which type you choose. N.B. Design the FSMD as a graph only, you do not need to design the control FSM and the datapath circuit. $5$ of $4$ Exam set continues next page while True: if $a>b: c=b \%$ a elif $a<b$ : $c=a$ * $b$ else: $c=$ $a / 3 a=a-1 b=b+4$